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idt79r4700 tm idt79rv4700 tm ? 1998 integrated device technology, inc. 1 integrated device technology, inc. features ? true 64-bit microprocessor - 64-bit integer operations - 64-bit floating-point operations - 64-bit registers - 64-bit virtual address space ? high-performance microprocessor - 260 dhrystone mips at 200mhz - 100 peak mflop/s at 200mhz - two-way set associative caches - simple 5-stage pipeline ? high level of integration - 64-bit, 200 mhz integer cpu - 64-bit floating-point unit - 16kb instruction cache - 16kb data cache - flexible mmu with large, fully associative tlb ? low-power operation - 3.3v power supply - dynamic power management - standby mode reduces internal power ? fully software and pin-compatible with 40 xx processor family ? available in 179-pin pga or 208-pin mquad ? available at 80-200mhz, with mode bit dependent out- put clock frequencies ? 64gb physical address space ? processor family for a wide variety of embedded applica- tions - lan switches -routers - color printers commercial temperature range january 1998 dsc xxx 3038 drw 01 the idt logo is a registered trademark and orion, r4640, rv4640, rv4650, r4650, r4700, rv4700, riscontroller, and riscore are t rademarks of integrated device technology, inc. windows is a registered trademark of microsoft corporation; unix is a registered trademark of at & t. 64-bit risc microprocessor block diagram read buffer integer register file integer/address adder data tlb virtual shifter/store aligner logic unit program counter pc incrementer branch adder load aligner floating-point unpacker/packer floating-point add/sub/cvt/div/sqrt integer divide floating-point/integer phase lock loop, clocks instruction tlb virtual joint tlb data set a data set b data tag a dtlb physical address buffer data tag b instruction tag a instruction tag b itlb physical store buffer write buffer dva iva instruction set a instruction set b multiply floating-point control integer control sysad ibus dbus coprocessor 0 system/memory control tag auxtag instruction select control instruction register register file
idt79r4700/rv4700 commercial temperature range 2 description the idt79r4700 64-bit risc microprocessor is both software and pin-compatible with the r4 xxx processor family. with 64-bit processing capabilities, the r4700 provides more computational power and data movement bandwidth than is delivered to typical embedded systems by 32-bit processors. through quick interrupt response times, fast algorithm execution speeds, and the ability to manipulate packet headers and make routing decisions quickly, the r4700 offers ideal internetworking solutions that are crucial for high-speed data switches and routers. the r4700 is upwardly software compatible with the idt79r3000 ? microprocessor family, including the idt riscontroller ? 79r3051 ? /r3052 ? /r3041 ? /r3081 ? / as well as the r4640 ? /r4650 ? and r5000 ? . an array of development tools facilitates rapid development of r4700- based systems, allowing a variety of customers access to the mips open architecture philosophy. this data sheet provides an overview of the r4700s cpu features and architecture. a more detailed descrip- tion of this processor is provided in the idt79r4600 and idt79r4700 risc processor hardware users manual , available from integrated device technology (idt). infor- mation on development support, applications notes and complementary products is available through your local idt sales representative. note that throughout this data sheet and any other idt materials for this device, the r4700 indicates a 5v part; rv4700 designates a reduced voltage (3v) part. data sheet revision history changes to version dated january 1996: deleted data on 150mhz speed for 5v part only. changes to version dated march 1997: upgraded 80 to 175 mhz speed specs from prelimi- nary to final. changes to version dated august 1997: upgraded speed to 200mhz on 3v part specs. added syncout to syncin delay parameters to ac characteristic tables. figure 1. r4700 pipeline stages i 0 1i 2i 1r 2r 1a 2a 1d 2d 1w 2w i 1 1i 2i 1r 2r 1a 2a 1d 2d 1w 2w i 2 1i 2i 1r 2r 1a 2a 1d 2d 1w ??? i 3 1i 2i 1r 2r 1a 2a 1d ??? i 4 1i 2i 1r 2r 1a ??? one cycle key to figure 1i-1r instruction cache access 2i instruction virtual-to-physical address translation in itlb 2a-2d data cache access and load align 1d data virtual-to-physical address translation in dtlb 1d-2d virtual-to-physical address translation in jtlb 2r register file read 2r bypass calculation 2r instruction decode 2r branch address calculation 1a issue or slip decision 1a-2a integer add, logical, shift 1a data virtual address calculation 2a store align 1a branch decision 2w register file write
idt79r4700/rv4700 commercial temperature range 3 hardware overview the r4700 processor family brings a high-level of inte- gration designed for high-performance computing. the r4700s key elements are briefly described below. a more detailed explanation of each subsystem is available in the users manual. pipeline the r4700 uses a simple 5-stage pipeline, similar to the pipeline structure implemented in the idt79r3000. this pipelines simplicity allows the r4700 to be lower cost and lower power than super-scalar or super-pipelined processors. however, unlike the r3000, the r4700 does virtual-to-physical translation in parallel with cache access. this capability allows the r4700 to operate at over three times the frequency of the r30xx and to support a larger tlb for address translation. the pipeline stages are shown in figure 1 on page 2. integer execution engine the r4700 implements the mips-iii instruction set architecture and is upwardly compatible with applications that run on earlier generation parts. implementation of the mips-iii architecture results in 64-bit operations, better code density, greater multi- processing support, improved performance for commonly used code sequences in operating system kernels and faster execution of floating-point intensive applications. all resource dependencies are made transparent to the programmer, insuring transportability among implementa- tions of the mips instruction set architecture. the mips integer unit implements a load/store archi- tecture with single cycle alu operations (logical, shift, add, sub) and an autonomous multiply/divide unit. register resources include: ? 32 general-purpose orthogonal integer registers ? hi/lo result registers, for the integer multiply/divide unit ? program counter also, the on-chip floating-point co-processor adds 32 floating-point registers and a floating-point control/status register. register file the r4700 has 32 general-purpose registers (shown in figure 2 ). these registers are used for scalar integer oper- ations and address calculation. the register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. alu the r4700 alu consists of the integer adder and logic unit. the adder performs address calculations in addition to arithmetic operations, and the logic unit performs all logical and shift operations. each of these units is highly optimized and can perform an operation in a single pipeline cycle. integer multiply/divide to perform integer multiply and divide operations, the r4700 uses the floating-point unit. the results of the opera- tion are placed in the hi and lo registers. the values can then be transferred to the general purpose register file using the mfhi/mflo instructions. to prevent the occur- rence of an interlock or stall, a required number (shown in table 1) of processor internal cycles must occur between an integer multiply or divide and a subsequent mfhi or mflo operation. floating-point co-processor the r4700 incorporates a complete floating-point co- processor on chip and includes a floating-point register file and execution units. the floating-point co-processor forms a seamless interface with the integer unit, decoding and executing instructions in parallel with the integer unit. floating-point units the r4700 floating-point execution units support single and double precision arithmetic, as specified in the ieee standard 754. the execution unit is separated into a mul- tiply unit and a combined add/convert/divide/square root unit. overlap of multiplies and add/subtract is supported. the multiplier is partially pipelined, allowing a new multiply to begin every four cycles. general purpose registers multiply/divide registers 63 0 063 0 r1 hi r2 63 0 ?lo ? ? program counter ?63 0 r29 pc r30 r31 figure 2. r4700 cpu registers operation 32-bit 64-bit mult 6 - 9 7 - 10 div 42 74 table 1. integer multiply/divide cycles
idt79r4700/rv4700 commercial temperature range 4 the r4700 maintains fully precise floating-point excep- tions while allowing both overlapped and pipelined opera- tions. precise exceptions are extremely important in mission-critical environments and highly desirable for debugging in any environment. the floating-point unit operations set includes floating- point add, subtract, multiply, divide, square root, conversion between fixed-point and floating-point format, conversion among floating-point formats and floating-point compare. these operations comply with the ieee standard 754. table 2 lists the latencies of some of the floating-point instructions in internal processor cycles. note that multi- plies are pipelined so that a new multiply can be initiated every four pipeline cycles floating-point general register file the floating-point register file is made up of thirty-two 64-bit registers. with the ldc1 and sdc1 instructions the floating-point unit can take advantage of the 64-bit wide data cache and issue a co-processor load or store double- word instruction in every cycle. the floating-point control register space contains two registers: one for determining configuration and revision information for the coprocessor and one for control and status information. these are primarily involved with diagnostic software, exception handling, state saving and restoring, and control of rounding modes. operation single precision double precision add 4 4 sub 4 4 mul 4 5 div 32 61 sqrt 31 60 cmp 3 3 fix 4 4 float 6 6 abs 1 1 mov 1 1 neg 1 1 lwc1, ldc1 2 2 swc1, sdc1 1 1 table 2. floating-point cycles 0 47 tlb (entries protected from tlbwr) entryhi 10* entrylo0 2* entrylo1 3* pagemask 5* wired 6* random 1* index 0* status 12* cause 13* epc 14* errorepc 30* count 9* compare 11* context 4* xcontext 20* prid 15* config 16* ta g h i 29* ta g l o 28* ecc 26* cacheerr 27* badvaddr 8* lladdr 17* * register number figure 3. the r4700 cpo registers
idt79r4700/rv4700 commercial temperature range 5 system control co-processor (cp0) the system control co-processor in the mips architec- ture is responsible for the virtual memory sub-system, the exception control system and the diagnostics capability of the processor. in the mips architecture, the system control co-processor (and thus the kernel software) is implementa- tion dependent. system control co-processor registers the r4700 incorporates all system control co- processor (cp0) registers, on-chip. these registers provide the path through which the virtual memory systems page mapping is examined and changed, exceptions are handled and operating modes are controlled (kernel vs. user mode, interrupts enabled or disabled, cache features). in addition, to aid in cache diagnostic testing and assist in data error detection, the r4700 includes registers to imple- ment a real-time cycle counting fac ility. figure 3 on page 4 shows the r4700s cp0 registers. virtual-to-physical address mapping to establish a secure environment for user processing, the r4700 provides the user, supervisor, and kernel modes of virtual addressing, available to system software. bits in a status register determine which virtual addressing mode is used. while in user mode, the r4700 provides a single, uniform virtual address space of 256gb (2gb for 32-bit address mode). when operating in the kernel mode, four distinct virtual address spacestotalling 1024gb (4gb in 32-bit address mode)are simultaneously available and are differentiated by the high-order bits of the virtual address. the r4700 processor also supports a supervisor mode in which the virtual address space is 256.5gb (2.5gb in 32-bit address mode), divided into three regions that are based on the high-order bits of the virtual address. if the r4700 is configured for 64-bit virtual addressing, the virtual address space layout is an upwardly compatible extension of the 32-bit virtual address space layout. figure 4 on page 6 shows the address space layout for the 32-bit virtual address operation. memory management unit (mmu) the memory management unit controls the virtual memory system page mapping. it consists of an instruction address translation buffer (the itlb), a data address trans- lation buffer (the dtlb), a joint tlb (the jtlb), and co- processor registers used for the virtual memory mapping sub-system. instruction tlb (itlb) the r4700 also incorporates a two-entry instruction tlb. each entry maps a 4kb page. the instruction tlb improves performance by allowing instruction address translation to occur in parallel with data address translation. when a miss occurs on an instruction address translation, the least-recently used itlb entry is filled from the jtlb. the operation of the itlb is invisible to the user. data tlb (dtlb) the r4700 also incorporates a four-entry data tlb. each entry maps a 4kb page. the data tlb improves performance by allowing data address translation to occur in parallel with instruction address translation. when a miss occurs on a data address translation, the dtlb is filled from the jtlb. the dtlb refill is pseudo-lru: the least recently used entry of the least recently used half is filled. the operation of the dtlb is invisible to the user. joint tlb (jtlb) for fast virtual-to-physical address decoding, the r4700 uses a large, fully associative tlb that maps 96 virtual pages to their corresponding physical addresses. the tlb is organized as 48 pairs of even-odd entries and maps a virtual address and address space identifier into the large, 64gb physical address space. two mechanisms are provided to assist in controlling the amount of mapped space and the replacement charac- teristics of various memory regions. first, the page size can be configured, on a per-entry basis, to map a page size of 4kb to 16mb (in multiples of 4). a cp0 register is loaded with the page size of a mapping, and that size is entered into the tlb when a new entry is written. thus, operating systems can provide special purpose maps; for example, a typical frame buffer can be memory mapped using only one tlb entry. the second mechanism controls the replacement algorithm, when a tlb miss occurs. the r4700 provides a random replacement algorithm to select a tlb entry to be written with a new mapping; however, the processor provides a mechanism whereby a system specific number of mappings can be locked into the tlb and avoid being randomly replaced. this facilitates the design of real-time systems, by allowing deterministic access to critical soft- ware. the joint tlb also contains information to control the cache coherency protocol for each page. specifically, each page has attribute bits to determine whether the coherency algorithm is uncached, non-coherent write-back, non- coherent write-through write-allocate or non-coherent write-through no write-allocate. non-coherent write-back is typically used for both code and data on the r4700; however, hardware-based cache coherency is not supported.
idt79r4700/rv4700 commercial temperature range 6 cache memory to keep the r4700s high-performance pipeline full and operating efficiently, the r4700 incorporates on-chip instruction and data caches that can be accessed in a single processor cycle. each cache has its own 64-bit data path and can be accessed in parallel. instruction cache the r4700 incorporates a two-way set associative on- chip instruction cache. this virtually indexed, physically tagged cache is 16kb in size and is protected with word parity. because the cache is virtually indexed, the virtual-to- physical address translation occurs in parallel with the cache access, further increasing performance by allowing these two operations to occur simultaneously. the tag holds a 24-bit physical address and valid bit and is parity protected. the instruction cache is 64-bits wide and can be refilled or accessed in a single processor cycle. for a peak instruction bandwidth of 800mb/sec at 200mhz, instruction fetches require only 32 bits per cycle. to reduce power dissipation, sequential accesses take advantage of the 64- bit fetch. to minimize the cache miss penalty, cache miss refill writes use 64 bits-per-cycle, and to maximize perfor- mance, the line size is eight instructions (32 bytes). data cache for fast, single cycle data access, the r4700 includes a 16kb on-chip data cache that is two-way set associative with a fixed 32-byte (eight words) line size. the data cache is protected with byte parity and its tag is protected with a single parity bit. it is virtually indexed and physically tagged to allow simultaneous address trans- lation and data cache access the normal write policy is writeback, which means that a store to a cache line does not immediately cause memory to be updated. this increases system performance by reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish before issuing a subsequent memory operation. software can however select write-through on a per-page basis when it is appro- priate, such as for frame buffers. associated with the data cache is the store buffer. when the r4700 executes a store instruction, this single- entry buffer gets written with the store data while the tag comparison is performed. if the tag matches, then the data is written into the data cache in the next cycle that the data cache is not accessed (the next non-load cycle). the store buffer allows the r4700 to execute a store instruction every processor cycle and to perform back-to-back stores without penalty. the data cache can provide 8 bytes each clock cycle, for a peak bandwidth of 1.6 gb/sec. write buffer writes to external memorywhether they are cache miss writebacks, stores to uncached or write-through addressesuse the on-chip write buffer. the write buffer holds a maximum of four 64-bit address and 64-bit data pairs. the entire buffer is used for a data cache writeback and allows the processor to proceed in parallel with memory updates. system interface the r4700 supports a 64-bit system interface. this interface operates from two clockstclock[1:0] and rclock[1:0]provided by the r4700, at some division of the internal clock. the system interface consists of a 64-bit address/data bus with eight check bits and a 9-bit command bus protected with parity. in addition, there are eight handshake signals and six interrupt inputs. the interface has a simple timing specification and is capable of transferring data between the processor and memory at a peak rate of 500mb/sec with a 67mhz bus. system address/data bus the 64-bit system address data (sysad) bus is used to transfer addresses and data between the r4700 and the rest of the system. it is protected with an 8-bit parity check bus, sysadc. the system interface is configurable to allow easier interfacing to memory and i/o systems of varying frequen- cies. the data rate and the bus frequency at which the r4700 transmits data to the system interface are program- mable via boot time mode control bits. also, the rate at which the processor receives data is fully controlled by the 0xffffffff 0xe0000000 kernel virtual address space (kseg3) mapped, 0.5gb 0xdfffffff supervisor virtual address space (sseg) mapped, 0.5gb 0xc0000000 0xbfffffff 0xa0000000 uncached kernel physical address space (kseg1) unmapped, 0.5gb 0x9fffffff 0x80000000 cached kernel physical address space (kseg0) unmapped, 0.5gb 0x7ffffff 0x00000000 user virtual address space (useg) mapped, 2.0gb figure 4. kernel mode virtual addressing (32-bit mode)
idt79r4700/rv4700 commercial temperature range 7 external device. therefore, either a low cost interface requiring no read or write buffering or a faster, high perfor- mance interface can be designed to communicate with the r4700. again, the system designer has the flexibility to make these price/performance trade-offs. system command bus the r4700 interface has a 9-bit system command (syscmd) bus. the command bus indicates whether the sysad bus carries an address or data. if the sysad carries an address, then the syscmd bus also indicates what type of transaction is to take place (for example, a read or write). if the sysad carries data, then the syscmd bus also gives information about the data (for example, this is the last data word transmitted, or the cache state of this data line is clean exclusive). the syscmd bus is bidirectional to support both processor requests and external requests to the r4700. processor requests are initiated by the r4700 and responded to by an external device. external requests are issued by an external device and require the r4700 to respond. the r4700 supports one to eight byte and block trans- fers on the sysad bus. in the case of a sub-doubleword transfer, the low-order three address bits give the byte address of the transfer, and the syscmd bus indicates the number of bytes being transferred. handshake signals there are six handshake signals on the system inter- face. two of these, rdrdy* and wrrdy* are used by an external device to indicate to the r4700 whether it can accept a new read or write transaction. the r4700 samples these signals before deasserting the address on read and write requests. extrqst* and release* are used to transfer control of the sysad and syscmd buses between the processor and an external device. when an external device needs to control the interface, it asserts extrqst*. the r4700 responds by asserting release* to release the system interface to slave state. validout* and validin* are used by the r4700 and the external device respectively to indicate that there is a valid command or data on the sysad and syscmd buses. the r4700 asserts validout* when it is driving these buses with a valid command or data, and the external device drives validin* when it has control of the buses and is driving a valid command or data. non-overlapping system interface the r4700 bus uses a non-overlapping system inter- face. this means that only one processor request may be outstanding at a time and that the request must be serviced by an external device before the r4700 issues another request. the r4700 can issue read and write requests to an external device, and an external device can issue read and write requests to the r4700. for processor read transaction the r4700 asserts validout* and simultaneously drives the address and read command on the sysad and syscmd buses. if the system interface has rdrdy* asserted, then the processor tristates its drivers and releases the system interface to slave state by asserting release*. the external device can then begin sending the data. figure 5 on page 9 shows a processor block read request and the external agent read response. the read latency is four cycles (validout* to validin*), and the response data pattern is ddxxdd. figure 6 on page 9 shows a processor block write. write reissue and pipeline write the r4700 implements additional write protocols that have been designed to improve performance. this imple- mentation doubles the effective write bandwidth. the write re-issue has a high repeat rate of two cycles per write. a write issues if wrrdy* is asserted two cycles earlier and is still asserted at the issue cycle. if it is not still asserted, the last write re-issues again. pipelined writes have the same two cycle per write repeat rate but can issue one additional write after wrrdy* de-asserts. they still follow the issue rule as r4x00 mode for other writes. external requests the r4700 responds to requests issued by an external device. the requests can take several forms. an external device may need to supply data in response to an r4700 read request or it may need to gain control over the system interface bus to access other resources which may be on that bus. it also may issue requests to the processor, such as a request for the r4700 to write to the r4700 interrupt register. the r4700 supports write, null, and read response external requests. boot-time options fundamental operational modes for the processor are initialized by the boot-time mode control interface. the boot-time mode control interface is a serial interface operat- ing at a very low frequency (masterclock divided by 256). the low-frequency operation allows the initialization infor- mation to be kept in a low-cost seriel eeprom; alterna- tively, the 20-or-so bits could be generated by the system interface asic or a simple pal. immediately after the v ccok signal is asserted, the processor reads a bit stream of 256 bits to initialize all fun- damental operational modes. after initialization is complete, the processor continues to drive the serial clock output, but no further initialization bits are read. jtag interface the r4700 supports the jtag interface pins, with the serial input connected to serial output. boundary scan is not supported.
idt79r4700/rv4700 commercial temperature range 8 boot-time modes the boot-time serial mode stream is defined in table 3. bit 0 is the first bit presented to the processor when v ccok is asserted; bit 255 is the last. power management cp0 is also used to control the power manage- ment for the r4700. this is the standby mode and can be used to reduce the power consumption of the internal core of the cpu. standby mode is entered by executing the wait instruction with the sysad bus idle and is exited by an interrupt. table 3. boot-time mode stream mode bit description mode bit description 0 reserved (must be zero) 14:13 output driver strength 10 ? 100% strength (fastest), 11 ? 83% strength, 00 ? 67% strength, 01 ? 50% strength (slowest) 4:1 writeback data rate 0 ? d, 1 ? ddx, 2 ? ddxx, 3 ? dxdx, 4 ? ddxxx, 5 ? ddxxxx, 6 ? dxxdxx, 7 ? ddxxxxxx, 8 ? dxxxdxxx, 9-15 reserved bit 15 0 -> tclock[0] enabled 1 -> tclock[0] disabled 7:5 clock divisor 0 ? 2, 1 ? 3, 2 ? 4, 3 ? 5, 4 ? 6, 5 ? 7, 6 ? 8, 7 reserved bit 16 0 -> tclock[1] enabled 1 -> tclock[1] disabled 80 ? little endian, 1 ? big endian bit 17 0 -> rclock[0] enabled 1 -> rclock[0] disabled 10:9 00 ? r4000 compatible, 01 ? reserved, 10 ? pipelined writes, 11 ? write re-issue bit 18 0 -> rclock[1] enabled 1 -> rclock[1] disabled 11 disable the timer interrupt on int[5]. 0 ? enabled 1 ? disabled 255:19 reserved (must be zero) 12 reserved (must be zero)
idt79r4700/rv4700 commercial temperature range 9 figure 5. processor block read figure 6. processor block write tclock rclock sysad addr data0 data1 data2 data3 syscmd read cdata cdata cdata ceod validout* validin* rdrdy* wrrdy* release* tclock rclock sysad addr data0 data1 data2 data3 syscmd validout* validin rdrdy* wrrdy* release* write cdata cdata cdata ceod
idt79r4700/rv4700 commercial temperature range 10 pin description table 4 contains a list of interface, interrupt and miscellaneous pins that are available on the r4700. note that signals marked with an asterisk are active when low. boundary scan is not supported. pin name type description system interface extrqst* i external request signals that the system interface needs to submit an external request. release* o release interface signals that the processor is releasing the system interface to slave state. rdrdy* i read ready signals that an external agent can now accept a processor read. wrrdy* i write ready signals that an external agent can now accept a processor write request. validin* i valid input signals that an external agent is now driving a valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. validout* o valid output signals that the processor is now driving a valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. sysad(63:0) i/o system address/data bus a 64-bit address and data bus for communication between the processor and an exter- nal agent. sysadc(7:0) i/o system address/data check bus an 8-bit bus containing parity check bits for the sysad bus during data bus cycles. syscmd(8:0) i/o system command/data identifier bus a 9-bit bus for command and data identifier transmission between the processor and an external agent. syscmdp i/o reserved system command/data identifier bus parity for the r4700 unused on input and zero on output. clock/control interface masterclock i master clock master clock input at one half the processor operating frequency. masterout o master clock out master clock output aligned with masterclock. rclock(1:0) o receive clocks two identical receive clocks at the system interface frequency. tclock(1:0) o transmit clocks two identical transmit clocks at the system interface frequency. ioout o reserved for future output always high. ioin i reserved for future input should be driven high. syncout o synchronization clock out synchronization clock output. must be connected to syncin through an interconnect that models the interconnect between masterout, tclock, rclock, and the external agent. syncin i synchronization clock in synchronization clock input. see syncout. fault* o fault always high. table 4. pin descriptions (page 1 of 2)
idt79r4700/rv4700 commercial temperature range 11 v cc piquiet v cc for pll quiet v cc for the internal phase locked loop. v ss piquiet v ss for pll quiet v ss for the internal phase locked loop. interrupt interface int*(5:0) i interrupt six general processor interrupts, bit-wise ored with bits 5:0 of the interrupt register. nmi* i non-maskable interrupt non-maskable interrupt, ored with bit 6 of the interrupt register. initialization interface v cco kiv cc is ok when asserted, this signal indicates to the r4700 that the power supply has been above the vcc minimum for more than 100 milliseconds and will remain stable. the assertion of v cco k initiates the reading of the boot-time-mode-control serial stream. coldreset* i cold reset this signal must be asserted for a power on reset or a cold reset. the clocks sclock, tclock, and rclock begin to cycle and are synchronized with the de-assertion edge of coldreset. coldreset must be de-asserted synchronously with masterout. reset* i reset this signal must be asserted for any reset sequence. it may be asserted synchronously or asynchronously for a cold reset, or synchronously to initiate a warm reset. reset must be de-asserted synchronously with masterout. modeclock o boot-mode clock serial boot-mode data clock output at the system clock frequency divided by two hun- dred fifty-six. modein i boot-mode data in serial boot-mode data input. pin name type description table 4. pin descriptions (page 2 of 2)
idt79r4700/rv4700 commercial temperature range 12 standby mode operations the r4700 provides a means to reduce the amount of power consumed by the internal core when the cpu would otherwise not be performing any useful operations. this is known as standby mode. entering standby mode executing the wait instruction enables interrupts and enters standby mode. when the wait instruction finishes the w pipe-stage, if the sysad bus is currently idle, the internal clocks will shut down, thus freezing the pipeline. the pll, internal timer, some of the input pin clocks (int[5:0]*, nmi*, extreq*, reset*, and cold- reset*), and the output clockstclock[1:0], rclock[1:0] syncout, modeclock and masteroutwill continue to run. if the conditions are not correct when the wait instruction finishes the w pipe-stage (such as the sysad bus is not idle), the wait is treated as a nop. once the cpu is in standby mode, any interrupt including the internally generated timer interruptwill cause the cpu to exit standby mode. thermal considerations the r4700 uses special packaging techniques to improve the thermal properties of high-speed proces- sors. the r4700 is packaged using cavity down pack- aging in a 179-pin pga package with integral thermal slug, and a 208-lead mquad qfp package. these packages effectively dissipate the power of the cpu, increasing device reliability. the r4700 uses the mquad package (the ms package), which is an all-aluminum package with the die attached to a normal copper lead frame mounted to the aluminum casing. due to the heat-spreading effect of the aluminum, the package allows for an efficient thermal transfer between the die and the case. the aluminum offers less internal resistance from one end of the package to the other, reducing the temperature gradient across the package and therefore presenting a greater area for convection and conduction to the pcb for a given temperature. even nominal amounts of airflow will dramatically reduce the junction tempera- ture of the die, resulting in cooler operation. the r4700 is guaranteed in a case temperature range of 0 to +85 c. the type of package, speed (power) of the device, and airflow conditions affect the equivalent ambient temperature conditions that will meet this specification. the equivalent allowable ambient temperature, t a , can be calculated using the thermal resistance from case to ambient ( ? ca ) of the given package. the following equation relates ambient and case temperatures: t a = t c - p * ? ca where p is the maximum power consumption at hot temperature, calculated by using the maximum i cc specifica- tion for the device. typical values for ? ca at various airflows are shown in table 5. table 5. thermal resistance ( ? ca) at various airflows note: the r4700 implements advanced power manage- ment to substantially reduce the average power dissipation of the device. this operation is described in the idt79r4600 & r4700 orion processor hardware users manual. ? ca airflow (ft/min) 0 200 400 600 800 1000 pga 167532.52 mquad 20129876
idt79r4700/rv4700 commercial temperature range 13 absolute maximum ratings (1) recommended operation temperature and supply voltage symbol rating rv4700 3.3v 5% r4700 5.0v 5% unit commercial commercial v term terminal voltage with respect to gnd C0.5 (2) to +4.6 C0.5 (2) to +7.0 v t c operating temperature (case) 0 to +85 0 to +85 c t bias case temperature under bias C55 to +125 C55 to +125 c t stg storage temperature C55 to +125 C55 to +125 c i in dc input current 20 (3) 20 (3) ma i out dc output current 50 50 (4) ma grade temperature gnd rv4700 r4700 v cc v cc commercial 0 c to +85 c (case) 0v 3.3v 5% 5.0v 5%
idt79r4700/rv4700 commercial temperature range 14 dc electrical characteristicsr4700 ( v cc = 5.0 5 %, t case = 0 c to +85 c) power consumptionr4700 parameter r4700 80 mhz r4700 100mhz r4700 133mhz conditions min max min max min max v ol 0.1v 0.1v 0.1v|i out |= 20ua v oh v cc - 0.1v v cc - 0.1v v cc - 0.1v v ol 0.4v 0.4v 0.4v|i out |= 4ma v oh 3.5v 3.5v 3.5v v il C0.5v 0.8v C0.5v 0.8v C0.5v 0.8v v ih 2.0v v cc + 0.5v 2.0v v cc + 0.5v 2.0v v cc + 0.5v i in 10ua 10ua 10ua 0 v in v cc c in 15pf 15pf 15pf c out 15pf 15pf 15pf i/o leak 20ua 20ua 20ua input/output leakage parameter r4700 80 mhz r4700 100mhz r4700 133mhz conditions typical max typical (9) max typical (9) max system condition: 80/20 mhz 100/25mhz 133/33mhz i cc standby 150ma b 175ma b 225ma b c l = 0pf (8) 215ma b 250ma b 325ma b c l = 50pf active 750ma b 850 ma b 875ma b 1000ma b 1175ma b 1300ma b c l = 0pf no sysad activity (8) 850ma b 1050ma b 975ma b 1200ma b 1275ma b 1500ma b c l = 50pf r4x00 compatible writes t c = 25 o c 850ma b 1250ma a 975ma b 1400ma a 1275ma b 1675ma a c l = 50pf pipelined writes or write re-issue t c = 25 o c a. these are the specifications idt tests to insure compliance. b. these are not tested. they are the result of engineering analysis and are provided for reference only.
idt79r4700/rv4700 commercial temperature range 15 ac electrical characteristicsr4700 (v cc =5.0v 5%; t case = 0 c to +85 c) clock parametersr4700 notes to ac/dc electrical characteristic tables: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v in minimum = -2.0v for pulse width less than 15ns. v in should not exceed v cc +0.5 volts. 3. when v in < 0v or v in > v cc 4. not more than one output should be shorted at a time. duration of the short should not exceed 30 seconds. 5. operation of the r4700 is only guaranteed with the phase lock loop enabled. 6. timings are measured from 1.5v of the clock to 1.5v of the signal. 7. capacitive load for all output timings is 50pf. 8. guaranteed by design. 9. typical integer instruction mix and cache miss rates. 10. operation of the rv4700 is only guaranteed with the phase lock loop enabled. 11. rise and fall times of the syncin signal must match those of masterclock to avoid the introduction of additional clock ske w. 12. guaranteed by design. 13. operation of the r4700 is only guaranteed with the phase lock loop enabled. 14. timings are measured from 1.5v of the clock to 1.5v of the signal. 15. capacitive load for all output timings is 50pf. 16. typical integer instruction mix and cache miss rates. 17. the maximum bus frequency (tclock) is 83 mhz. parameter symbol test conditions r4700 80mhz r4700 100mhz r4700 133mhz units min max min max min max masterclock high t mchigh transition t mcrise 443 ns masterclock low t mclow transition t mcfall 443 ns masterclock frequency (5) 25 40 25 50 25 67 mhz masterclock period t mcp 2540 2040 15 40 ns clock jitter for master- clock t jitterin (8) 250 250 250 ps clock jitter for masterout, syncout, tclock, rclock t jitterout (8) 500 500 500 ps masterclock rise time t mcrise (8) 5.55 4ns masterclock fall time t mcfall (8) 5.55 4ns modeclock period t modeckp (8) 256*t mcp 256*t mcp 256*t mcp ns jtag clock period t jtagckp (8) 4*t mcp 4*t mcp 4*t mcp ns
idt79r4700/rv4700 commercial temperature range 16 system interface parametersr4700 (6) boot-time interface parametersr4700 capacitive load derationr4700 parameter symbol test conditions r4700 80mhz r4700 100mhz r4700 133mhz units min max min max min max data output (7) t do mode 14..13 = 10 (fastest) 1.0* 9 1.0* 9 1.0* 9 ns mode 14..13 = 01 (slowest) 2.0* 15 2.0* 15 2.0* 12 ns data setup t ds t rise = 5ns t fall = 5ns 3.5 3.5 3.5 ns data hold t dh 1.5 1.5 1.5 ns *values are guaranteed by design. parameter symbol test conditions r4700 80mhz r4700 100mhz r4700 133mhz units min max min max min max mode data setup t ds 3 3 3 master clockcycle mode data hold t dh 0 0 0 master clockcycle parameter symbol r4700 80mhz r4700 100mhz r4700 133mhz units min max min max min max load derate c ld 2 2 2 ns/25pf
idt79r4700/rv4700 commercial temperature range 17 dc electrical characteristicsrv4700 (v cc = 3.3 5 %, t case = 0 c to +85 c) power consumptionrv4700 parameter rv4700 100mhz rv4700 133mhz conditions min max min max v ol 0.1v 0.1v |i out |= 20ua v oh v cc - 0.1v v cc - 0.1v v ol 0.4v 0.4v |i out |= 4ma v oh 2.4v 2.4v v il C0.5v 0.2v cc C0.5v 0.2v cc v ih 0.7v cc v cc + 0.5v 0.7v cc v cc + 0.5v i in 10ua 10ua 0 v in v cc c in 15pf 15pf c out 15pf 15pf i/o leak 20ua 20ua input/output leakage parameter rv4700 150mhz rv4700 175mhz rv4700 200mhz conditions min max min max min max v ol 0.1v 0.1v 0.1v |i out |= 20ua v oh v cc - 0.1v v cc - 0.1v v cc - 0.1v v ol 0.4v 0.4v 0.4v |i out |= 4ma v oh 2.4v 2.4v 2.4v v il C0.5v 0.2v cc C0.5v 0.2v cc C0.5v 0.2v cc v ih 0.7v cc v cc + 0.5v 0.7v cc v cc + 0.5v 0.7v cc v cc + 0.5v i in 10ua 10ua 10ua 0 v in v cc c in 15pf 15pf 15pf c out 15pf 15pf 15pf i/o leak 20ua 20ua 20ua input/output leakage parameter rv4700 100mhz rv4700 133mhz rv4700 150mhz conditions typical (9) max typical (9) max typical (9) max system condition 100/25mhz 133/33mhz 150/38mhz i cc standby 125ma b 175ma b 200ma b c l = 0pf (8 175ma b 225ma b 250ma b c l = 50pf active 575ma b 875ma b 775ma b 1150ma b 875ma b 1300ma b c l = 0pf, no sysad activity (8 650ma b 1100ma b 850ma b 1375ma b 950ma b 1550ma b c l = 50pf r4x00 compatible writes, t c = 25 o c (8) 650ma b 1275ma a 850ma b 1525ma a 950ma b 1725ma a c l = 50pf pipelined writes or write re-issue, t c = 25 o c
idt79r4700/rv4700 commercial temperature range 18 parameter rv4700 175mhz rv4700 200mhz conditions typical (9) max typical (9) max system condition 175/44mhz 200/50mhz i cc standby 200ma b 200ma b c l = 0pf (8) 250ma b 250ma b c l = 50pf active 1025ma b 1500ma b 1025ma b 1500ma b c l = 0pf, no sysad activity (8) 1200ma b 1800ma b 1200ma b 1800ma b c l = 50pf r4x00 compatible writes, t c = 25 o c (8) 1200ma b 2000ma a 1200ma b 2000ma a c l = 50pf pipelined writes or write re-issue, t c = 25 o c a. these are the specifications idt tests to insure compliance. b. these are not tested. they are the result of engineering analysis and are provided for reference only.
idt79r4700/rv4700 commercial temperature range 19 ac electrical characteristics rv4700 (v cc =3.3v 5%; t case = 0 c to +85 c) clock parameters parameter symbol test conditions rv4700 100mhz rv4700 133mhz rv4700 150mhz units min max min max min max masterclock high t mchigh transition t mcrise/fall 4 3 3 ns masterclock low t mclow transition t mcrise/fall 4 3 3 ns masterclock fre- quency (16) 25 50 25 67 25 75 mhz masterclock period t mcp 2040 1540 13.340 ns clock jitter for master- clock t jitterin (12) 250250 250 ps clock jitter for masterout, syncout, tclock, rclock t jitterout (12) 500500 500 ps masterclock rise time t mcrise (12) 543.5ns masterclock fall time t mcfall (12) 543.5ns modeclock period t modeckp 256*t mcp 256*t mcp 256*t mcp ns parameter symbol test conditions rv4700 175mhz (17) rv4700 200mhz (17) units min max min max masterclock high t mchigh transition t mcrise/fall 3 3 ns masterclock low t mclow transition t mcrise/fall 3 3 ns masterclock frequency (16) 25 87.5 25 100 mhz masterclock period t mcp 11.4401040ns clock jitter for masterclock t jitterin (12) 250 250 ps clock jitter for masterout, syncout, tclock, rclock t jitterout (12) 500 500 ps masterclock rise time t mcrise (12) 3.53.5ns masterclock fall time t mcfall (12) 3.53.5ns modeclock period t modeckp 256*t mcp 256*t mcp ns syncout to syncin delay t sync (8) (11) t mcp -2 t mcp -2 ns
idt79r4700/rv4700 commercial temperature range 20 system interface parametersrv4700 (13) boot-time interface parametersrv4700 capacitive load derationrv4700 parameter symbol test conditions rv4700 100mhz rv4700 133mhz rv4700 150mhz units min max min max min max data output (14) t dm = min t do = max mode 14..13 = 10 (fastest) 1.0 9 1.0 9 1.0 8 ns mode 14..13 = 01 (slowest) 2.0 15 2.0 12 2.0 12 ns data setup t ds t rise = 3ns t fall = 3ns 3.5 3.5 3.5 ns data hold t dh 1.5 1.5 1.5 ns parameter symbol test conditions rv4700 175mhz rv4700 200mhz units min max min max data output (7) t dm = min t do = max mode 14..13 = 10 (fastest) 1.0 8 1.0 8 ns mode 14..13 = 01 (slowest) 2.0 12 2.0 12 ns data setup t ds t rise = 3ns t fall = 3ns 3.5 3.5 ns data hold t dh 1.5 1.5 ns parameter symbol test conditions rv4700 100mhz rv4700 133mhz rv4700 150mhz units min max min max min max mode data setup t ds 3 3 3 master clock cycle mode data hold t dh 0 0 0 master clock cycle parameter symbol test conditions rv4700 175mhz rv4700 200mhz units min max min max mode data setup t ds 3 3 master clock cycle mode data hold t dh 0 0 master clock cycle parameter symbol rv4700 100mhz rv4700 133mhz rv4700 150mhz units min max min max min max load derate c ld 2 2 2 ns/25pf parameter symbol rv4700 175mhz rv4700 200mhz units min max min max load derate c ld 22ns/25pf
idt79r4700/rv4700 commercial temperature range 21 physical specifications 208-pin mquad 104 105 1 208 156 157 53 52 pq208-2 ms208 top view
idt79r4700/rv4700 commercial temperature range 22 physical specifications pga r4000, r4400 pc pinout bottom 1234 56 78 9101112131415161718 v u t r p n m l k j h g f e d c b a 2884 drw 12 1234 56 78 9101112131415161718 v u t r p n m l k j h g f e d c b a bottom r4700 pinout
idt79r4700/rv4700 commercial temperature range 23 r4700 mquad package pin-out ? ? n.c. pins should be left floating for maximum flexibility and compatibility with future designs. pin function pin function pin function pin function 1 n.c. 53 n.c. 105 n.c. 157 n.c. 2 n.c. 54 n.c. 106 n.c. 158 n.c. 3 vss 55 syscmd2 107 n.c. 159 rclock0 4 vcc 56 sysad36 108 n.c. 160 rclock1 5 sysad45 57 sysad4 109 vcc 161 syncout 6 sysad13 58 syscmd1 110 vss 162 sysad30 7 fault* 59 vss 111 sysad21 163 vcc 8 sysad44 60 vcc 112 sysad53 164 vss 9 vss 61 sysad35 113 rdrdy* 165 sysad62 10 vcc 62 sysad3 114 modein 166 masterout 11 sysad12 63 syscmd0 115 sysad22 167 sysad31 12 syscmdp 64 sysad34 116 sysad54 168 sysad63 13 sysad43 65 vss 117 vcc 169 vcc 14 sysad11 66 vcc 118 vss 170 vss 15 vss 67 n.c. 119 release* 171 vccok 16 vcc 68 n.c. 120 sysad23 172 sysadc3 17 syscmd8 69 sysad2 121 sysad55 173 sysadc7 18 sysad42 70 int5* 122 nmi* 174 vcc 19 sysad10 71 sysad33 123 vcc 175 vss 20 syscmd7 72 sysad1 124 vss 176 n.c. 21 vss 73 vss 125 sysadc2 177 n.c. 22 vcc 74 vcc 126 sysadc6 178 n.c. 23 sysad41 75 int4* 127 vcc 179 n.c. 24 sysad9 76 sysad32 128 sysad24 180 n.c. 25 syscmd6 77 sysad0 129 vcc 181 vccp 26 sysad40 78 int3* 130 vss 182 vssp 27 n.c. 79 vss 131 sysad56 183 n.c. 28 n.c. 80 vcc 132 n.c. 184 n.c. 29 vss 81 int2* 133 sysad25 185 masterclock 30 vcc 82 sysad16 134 sysad57 186 vcc 31 sysad8 83 sysad48 135 vcc 187 vss 32 syscmd5 84 int1* 136 vss 188 syncin 33 sysadc4 85 vss 137 ioout 189 vcc 34 sysadc0 86 vcc 138 sysad26 190 vss 35 vss 87 sysad17 139 sysad58 191 n.c. 36 vcc 88 sysad49 140 ioin 192 sysadc5 37 syscmd4 89 int0* 141 vcc 193 sysadc1 38 sysad39 90 sysad18 142 vss 194 jtdi 39 sysad7 91 vss 143 sysad27 195 vcc 40 syscmd3 92 vcc 144 sysad59 196 vss 41 vss 93 sysad50 145 coldreset* 197 sysad47 42 vcc 94 validin* 146 sysad28 198 sysad15 43 sysad38 95 sysad19 147 vcc 199 jtdo 44 sysad6 96 sysad51 148 vss 200 sysad46 45 modeclock 97 vss 149 sysad60 201 vcc 46 wrrdy* 98 vcc 150 reset* 202 vss 47 sysad37 99 validout* 151 sysad29 203 sysad14 48 sysad5 100 sysad20 152 sysad61 204 n.c. 49 vss 101 sysad52 153 vcc 205 tclock0 50 vcc 102 extrqst* 154 vss 206 tclock1 51 n.c. 103 n.c. 155 n.c. 207 n.c. 52 n.c. 104 n.c. 156 n.c. 208 n.c.
idt79r4700/rv4700 commercial temperature range 24 r4700 pga package pin-out ? ? n.c. pins should be left floating for maximum flexibility and compatibility with future designs. function pin function pin function pin coldreset* t14 sysad36 c3 vcc b18 extrqst* u2 sysad37 b3 vcc c1 fault* b16 sysad38 c6 vcc d18 reserved o (nc) u10 sysad39 c7 vcc f1 reserved i (vcc) t9 sysad40 c10 vcc g18 ioin t13 sysad41 c11 vcc h1 ioout u12 sysad42 b13 vcc j18 int0 n2 sysad43 a15 vcc k1 int1 l3 sysad44 c15 vcc l18 int2 k3 sysad45 b17 vcc m1 int3 j3 sysad46 e17 vcc n18 int4 h3 sysad47 f17 vcc r1 int5 f2 sysad48 l2 vcc t18 masterclock j17 sysad49 m3 vcc u1 masterout p17 sysad50 n3 vcc v3 modeclock b4 sysad51 r2 vcc v6 modein u4 sysad52 t3 vcc v8 nmi u7 sysad53 u3 vcc v10 rclock0 t17 sysad54 t6 vcc v12 rclock1 r16 sysad55 t7 vcc v14 rdrdy* t5 sysad56 t10 vcc v17 release v5 sysad57 t11 vss a3 reset* u16 sysad58 u13 vss a6 syncin j16 sysad59 v15 vss a8 syncout p16 sysad60 t15 vss a10 sysad0 j2 sysad61 u17 vss a12 sysad1 g2 sysad62 n16 vss a14 sysad2 e1 sysad63 n17 vss a17 sysad3 e3 sysadc0 c8 vss a18 sysad4 c2 sysadc1 g17 vss b1 sysad5 c4 sysadc2 t8 vss c18 sysad6 b5 sysadc3 l16 vss d1 sysad7 b6 sysadc4 b8 vss f18 sysad8 b9 sysadc5 h16 vss g1 sysad9 b11 sysadc6 u8 vss h18 sysad10 c12 sysadc7 l17 vss j1 sysad11 b14 syscmd0 e2 vss k18 sysad12 b15 syscmd1 d3 vss l1 sysad13 c16 syscmd2 b2 vss m18 sysad14 d17 syscmd3 a5 vss n1 sysad15 e18 syscmd4 b7 vss p18 sysad16 k2 syscmd5 c9 vss r18 sysad17 m2 syscmd6 b10 vss t1 sysad18 p1 syscmd7 b12 vss u18 sysad19 p3 syscmd8 c13 vss v1 sysad20 t2 syscmdp c14 vss v2 sysad21 t4 tclock1 c17 vss v4 sysad22 u5 tclock0 d16 vss v7 sysad23 u6 vccok m17 vss v9 sysad24 u9 validin* p2 vss v11 sysad25 u11 validout* r3 vss v13 sysad26 t12 wrrdy* c5 vss v16 sysad27 u14 vccp k17 vss v18 sysad28 u15 vssp k16 jtms e16 sysad29 t16 vcc a2 jtdo f16 sysad30 r17 vcc a4 jtdi g16 sysad31 m16 reserved i (vcc) a7 jtck h17 sysad32 h2 vcc a9 sysad33 g3 vcc a11 sysad34 f3 vcc a13 sysad35 d2 vcc a16
idt79r4700/rv4700 commercial temperature range 25 integrated device technology, inc. reserves the right to make changes to the specifications in this data sheet in order to impr ove design or performance and to supply the best possible product. integrated device technology, inc. 2975 stender way, santa clara, ca 95054-3090 telephone: (408) 727-6116 fax 408-492-8674 ordering information valid combinations idt79r4700 - 80,100, 133 pga, mquad package idt79rv4700 -100, 133, 150, 175, 200 pga, mquad package yy configuration 999 speed a package a process/ temperature range blank commercial g ms pga 179 208-pin mquad 100 133 150 175 3.3v 5% xxxx device type rv enhanced 64-bit cpu idt79 100 mhz 133 mhz 150 mhz 175 mhz 4700 5.0v 5% r 80 80 mhz (0c to +85c (case)) 200 200 mhz

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